One board design, repeated around the head

The 48 contact boards and 16 controllers all have different shapes, so JLC charges 66 setup fees. These layouts swap them for one small identical tile, or one tile plus a filler. Each tile carries its own pins, amplifiers and a $0.40 MCU whose ADC does the conversion, and the tiles daisy-chain into the hub's existing 16 ports. The shape of the head now lives in the printed shell. Layouts are packed on the repo's headform (exo/head.py, 100/80/102 mm, above the cuff line, clear of the hub); costs use the repo's own JLC fee model and live JLC prices.

Layouts

All layouts side by side

Pin-gap spread is the largest difference, under any one tile, between the closest and farthest scalp point beneath its pins (board flat, tangent at its centre). Up to about 0.5 mm, rigid pins can work if each tile floats on a soft pad; above that, each pin needs its own spring. Designs counts the tile designs plus the hub and the camera board. Costs are everything for one helmet, spares included: boards, assembly, parts, cameras, battery, shell, beanie.

Where the money goes

What's on a tile

pin ─ 100k ─ 100k ─┬─ 1 µF ─┬─ TLV333, gain 200 ─ RC ─► MCU ADC in (scalp face) 2.2M to REF Rg returned to buffered REF REF (from the hub port) ─ TLV333 buffer ─► every channel's Rg, and ADC in #10 MCU: CH32V203G6U6, 12-bit 1 MSPS ADC, 10 inputs, QFN-28 4×4 mm link: 2 × 12-way 0.5 mm FPC (in, out), the hub port's pinout VIN · GND · REF · CLK · SYNC · data down · data up

Same parts as today, minus the expensive ones. The TLV333 behind every pin stays, but it now also amplifies (gain 200) instead of only buffering. That brings the signal up to where the MCU's 12-bit ADC can digitise it, and oversampling about 200× takes out the rest of the ADC noise. The ADS131M08 ($6.62 for 8 channels), the RP2040 controllers, the DF40 stacks and the PAT9125 optics all go.

Chains, not controllers. Each tile forwards the frames from the tiles behind it and adds its own. Each chain's first tile plugs into a hub port with the cable used today, so the hub board stays as it is and only needs new firmware. CLK and SYNC already run to every port, so every tile samples on the hub's clock.

Pins

Noise (per channel, 0.5–100 Hz)

A 1 MΩ dry contact dominates either way: its thermal noise is 1.29 µV and the follower's current noise across it is 1.0 µV. Today's 1.0 µV converter noise is replaced by a gain of 200 followed by an oversampled 12-bit ADC, which adds about 0.4 µV. SNR is quoted for a 10 µV rms signal. These are paper numbers; nothing has been measured on a head yet, today's design included.

Trapezoid caps, as in the launch video

The last three tabs. Each ring is a band of trapezoids meeting edge to edge. The band's bottom edge runs at a fixed distance above the cuff, measured along the scalp, so every ring is complete and keeps one height all the way round. Each facet's side edges run straight uphill. The rings don't keep their shape as they rise: the cuff dips at the back for the neck and hub, so toward the top they stretch into a ridge running front to back. Each ring therefore uses two boards: one trapezoid for the sides, where the rings run parallel, and a steeper end trapezoid for the front and back. Every board is checked to lie inside its facet with a 0.8 mm gap, and no two boards overlap anywhere. A few 7-pin hexagons close the crown. Pins sit on a honeycomb lattice inside each board, at 5.3 mm spacing and 2.4 mm in from every edge.

Shapes that lost (first pass: fixed angle bands)

Trapezoid rings cover more of the scalp by area, but they carry fewer pins. A slanted edge wastes the inset, and a rectangular pin grid can't fill a taper. Each ring's shape also has to fit the smallest cell in that ring, because the head is 200 mm long but 160 mm wide. Squares and hexagons hold an exact pin grid edge to edge, and free rotation lets them fill the gaps between rings.

What still needs a bench